Microelectronic substrates with integrated devices

ABSTRACT

A microelectronic substrate including at least one microelectronic device disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic devices, or a plurality microelectronic devices encapsulated without the microelectronic substrate core. At least one conductive via extended through the substrate, which allows electrical communication between opposing sides of the substrate. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic device, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.

RELATED APPLICATIONS

[0001] This is a continuation-in-part of application Ser. No.09/692,908, filed Oct. 19, 2000, which is a continuation-in-part ofapplication Ser. No. 09/640961, filed Aug. 16, 2000.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to apparatus and processes for thefabrication of microelectronic substrates. In particular, the presentinvention relates to a fabrication technology that encapsulates at leastone microelectronic device within a microelectronic substrate core orthat encapsulates at least one microelectronic device (without amicroelectronic substrate core) to form a two-sided microelectronicsubstrate or a two layer microelectronic substrate.

[0004] 2. State of the Art

[0005] Substrates which connect individual microelectronic devices existin virtually all recently manufactured electronic equipment. Thesesubstrates are generally printed circuit boards. Printed circuit boardsare basically dielectric substrates with metallic traces formed in orupon the dielectric substrate. One type of printed circuit board is asingle-sided board. As shown in FIG. 23, single-sided board 300 consistsof a dielectric substrate 302, such as an FR4 material, epoxy resins,polyimides, triazine resins, and the like, having conductive traces 304,such as copper, aluminum, and the like, on one side (i.e., first surface306), wherein the conductive traces 304 electrically interconnectmicroelectronic devices 308 (shown as flip-chips) attached to the firstsurface 306. However, single-sided boards 300 result in relatively longconductive traces 304, which, in turn, result in slower speeds andperformance. Single-sided boards 300 also require substantial surfacearea for the routing of the conductive traces 304 to interconnect thevarious microelectronic devices 308, which increases the size of theresulting assembly.

[0006] It is, of course, understood that the depiction of the dielectricsubstrate 302, the conductive traces 304, and the microelectronicdevices 308 in FIG. 23 (and subsequently FIGS. 24 and 25) are merely forillustration purposes and certain dimensions are greatly exaggerated toshow the concept, rather than accurate details thereof.

[0007] Double-sided boards 310 were developed to help alleviate theproblem with relatively long conductive traces. As shown in FIG. 24, thedouble-sided board 310 comprises a dielectric substrate 302 havingconductive traces 304 on the dielectric substrate first surface 306 andon a dielectric substrate second surface 312. At least one electricallyconductive via 314 extends through the dielectric substrate 302 toconnect at least one conductive trace 304 on the first surface 306 withat least one conductive trace 304 on the second surface 312. Thus, themicroelectronic devices 308 on the dielectric substrate first surface306 and on the dielectric substrate second surface 312 may be inelectrical communication. The electrically conductive vias 314 aregenerally plated through-hole vias and may be formed in any manner knownin the art.

[0008]FIG. 25 illustrates another board design, known as a multi-layerboard 320. A multi-layer board 320 comprises two or more pieces ofdielectric material (shown as first dielectric material 322 and seconddielectric material 324) with conductive traces 304 thereon andtherebetween with electrically conductive vias 314 formed through thefirst dielectric material 322 and the second dielectric material 324.This design allows for shorter traces and reduced surface arearequirements for conductive trace 304 routing.

[0009] Although such boards have been adequate for past and currentmicroelectronic device applications, the need for higher performance andshorter traces of substrate boards increases as the speed andperformance of the microelectronic devices increase. Therefore, it wouldbe advantageous to develop new substrates/boards, which achieve higherspeed and performance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] While the specification concludes with claims particularlypointing out and distinctly claiming that which is regarded as thepresent invention, the advantages of this invention can be more readilyascertained from the following description of the invention when read inconjunction with the accompanying drawings, in which:

[0011]FIG. 1 is an oblique view of a microelectronic substrate core,according to the present invention;

[0012]FIG. 2 is a top plan view of a microelectronic substrate corehaving examples of alternate microelectronic substrate core openings,according to the present invention;

[0013]FIG. 3 is a side cross-sectional view of a microelectronicsubstrate core abutted to a protective film, according to the presentinvention;

[0014]FIG. 4 is a side cross-sectional view of microelectronic devicesdisposed within openings of the microelectronic substrate core, whichalso abuts the protective film, according to the present invention;

[0015]FIG. 5 is a side cross-sectional view of the assembly of FIG. 4after encapsulation, according to the present invention;

[0016]FIG. 6 is a side cross-sectional view of the assembly of FIG. 5after the protective film has been removed, according to the presentinvention;

[0017]FIG. 7 is a side cross-sectional view of multiple microelectronicdevices within a single core opening;

[0018]FIG. 8 is a side cross-sectional view of the assembly of FIG. 6without a microelectronic substrate core, according to the presentinvention;

[0019]FIG. 9 is a dual substrate assembly, according to the presentinvention;

[0020]FIG. 10 illustrates the dual substrate assembly of FIG. 9 havingconductive via formed therethrough, according to the present invention;

[0021]FIG. 11 is an enlarged view of the dual substrate assembly of FIG.10, according to the present invention;

[0022]FIG. 12 illustrates the dual substrate assembly of FIG. 11 havinginterconnection layers formed on opposing surfaces thereof, according tothe present invention;

[0023]FIG. 13 illustrates the dual substrate assembly of FIG. 12 havingconductive interconnects formed on the interconnection layers, accordingto the present invention;

[0024]FIG. 14 is a view of FIG. 13 illustrating a plurality of themicroelectronic devices encapsulated in each microelectronic substratecore, according to the present invention;

[0025]FIG. 15 illustrates microelectronic devices 174 and 174′ attachedto the assembly of FIG. 14, according to the present invention;

[0026]FIG. 16 illustrates the assembly of FIG. 15 attached to anexternal system board through external attachment feature, according tothe present invention;

[0027]FIG. 17 illustrates the dual substrate assembly of FIG. 15 havinga heat dissipation device between the first substrate and the secondsubstrate, according to the present invention;

[0028]FIG. 18 is a single substrate microelectronic assembly, accordingto the present invention;

[0029]FIG. 19 illustrates the single substrate microelectronic assemblyhaving heat dissipation devices attached to the back surface of themicroelectronic devices encapsulated therein, according to the presentinvention;

[0030]FIG. 20 illustrates multiple single substrate microelectronicassemblies of FIG. 19 interconnected to form a layered microelectronicsubstrate assembly, according to the present invention;

[0031]FIG. 21 is an alternate embodiment of the layered microelectronicsubstrate assembly of FIG. 20, according to the present invention;

[0032]FIG. 22 is an alternate embodiment of the layered microelectronicsubstrate assembly of FIG. 21, according to the present invention;

[0033]FIG. 23 is a cross-sectional view of a single-sided board, asknown in the art;

[0034]FIG. 24 is a cross-sectional view of a double-sided board, asknown in the art; and

[0035]FIG. 25 is a cross-sectional view of a multi-layer board, as knownin the art.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT

[0036] In the following detailed description, reference is made to theaccompanying drawings that show, by way of illustration, specificembodiments in which the invention may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention. It is to be understood that the variousembodiments of the invention, although different, are not necessarilymutually exclusive. For example, a particular feature, structure, orcharacteristic described herein, in connection with one embodiment, maybe implement within other embodiments without departing from the spiritand scope of the invention. In addition, it is to be understood that thelocation or arrangement of individual elements within each disclosedembodiment may be modified without departing from the spirit and scopeof the invention. The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the appended claims, appropriately interpreted, alongwith the full range of equivalents to which the claims are entitled. Inthe drawings, like numerals refer to the same or similar functionalitythroughout the several views.

[0037] The present invention includes a substrate fabrication technologythat places at least one microelectronic device within at least oneopening in a microelectronic substrate core and secures themicroelectronic device(s) within the opening(s) with an encapsulationmaterial or that encapsulates at least one microelectronic device withinan encapsulation material without a microelectronic substrate core toform a microelectronic substrate. At least one conductive via extendedthrough the substrate, which allows electrical communication betweenopposing sides of the substrate. Interconnection layers of dielectricmaterials and conductive traces are then fabricated on themicroelectronic device(s), the encapsulation material, and themicroelectronic substrate core (if present) to form a microelectronicsubstrate. Two microelectronic substrates may be attached to one anothereither before or after the formation of the interconnection layers.

[0038] The technical advantage of this invention is that it enables themicroelectronic substrate to be built around the microelectronicdevice(s), which results in a shorter interconnect distance betweenmicroelectronic devices within the microelectronic substrate and othermicroelectronic devices attached thereto. This, in turn, results inhigher speed and performance. Furthermore, the microelectronic substrateof the present invention may also result in a smaller form factor, whichis well suited to mobile systems (i.e., laptop computers, handhelddevices, personal digital assistants, etc.).

[0039]FIG. 1 illustrates a microelectronic substrate core 102 used tofabricate a microelectronic substrate. The microelectronic substratecore 102 preferably comprises a substantially planar material. Thematerial used to fabricate the microelectronic substrate core 102 mayinclude, but is not limited to, a Bismaleimide Triazine (“BT”) resinbased laminate material, an FR4 laminate material (a flame retardingglass/epoxy material), various polyimide laminate materials, ceramicmaterial, and the like, and metallic materials (such as copper) and thelike. The microelectronic substrate core 102 has at least one opening104 extending therethrough from a first surface 106 of themicroelectronic substrate core 102 to an opposing second surface 108 ofthe microelectronic substrate core 102. As shown in FIG. 2, theopening(s) 104 may be of any shape and size including, but not limitedto, rectangular/square 104 a, rectangular/square with rounded corners104 b, and circular 104 c. The only limitation on the size and shape ofthe opening(s) 104 is that they must be appropriately sized and shapedto house a corresponding microelectronic device therein, as will bediscussed below. It is, of course, understood that the openings 104 neednot be in a regular array/spacing, but may be placed wherever desiredwithin the microelectronic substrate core 102.

[0040]FIG. 3 illustrates the microelectronic substrate core firstsurface 106 abutting a protective film 112. The protective film 112 ispreferably a substantially flexible material, such as Kapton® polyimidefilm (E. I. du Pont de Nemours and Company, Wilmington, Del.), but maybe made of any appropriate material, including metallic films. In apreferred embodiment, the protective film 112 would have substantiallythe same coefficient of thermal expansion (CTE) as the microelectronicsubstrate core. FIG. 4 illustrates microelectronic device 114, eachhaving an active surface 116 and a back surface 118, placed incorresponding openings 104 of the microelectronic substrate core 102.The microelectronic device 114 may be any known active or passivemicroelectronic device including, but not limited to, logic (CPUs),memory (DRAM, SRAM, SDRAM, etc.), controllers (chip sets), capacitors,resistors, inductors, and the like.

[0041] In a preferred embodiment (illustrated), the thickness 117 of themicroelectronic substrate core 102 and the thickness 115 of themicroelectronic device 114 are substantially equal. The microelectronicdevice 114 are each placed such that their active surfaces 116 abut theprotective film 112. The protective film 112 may have an adhesive, suchas silicone or acrylic, which attaches to the microelectronic substratecore first surface 106 and the microelectronic device active surface116. This adhesive-type film may be applied prior to placing themicroelectronic device 114 and microelectronic substrate core 102 in amold, liquid dispense encapsulation system (preferred), or other pieceof equipment used for the encapsulation process. The protective film 112may also be a non-adhesive film, such as a ETFE(ethylene-tetrafluoroethylene) or Teflon® film, which is held on themicroelectronic device active surface 116 and the microelectronicsubstrate core first surface 106 by an inner surface of the mold orother piece of equipment during the encapsulation process.

[0042] The microelectronic device 114 is then encapsulated with anencapsulation material 122, such as plastics, resins, epoxies,elastomeric (i.e., rubbery) materials, and the like. As shown in FIG. 5,the encapsulation material 122 is disposed in portions of the opening(s)104 not occupied by the microelectronic device 114. The encapsulation ofthe microelectronic device 114 may be achieved by any known process,including but not limited to transfer and compression molding, anddispensing. The encapsulation material 122 secures the microelectronicdevice 114 within the microelectronic substrate core 102 and providesmechanical rigidity for the resulting structure and provides surfacearea for the subsequent build-up of trace layers.

[0043] After encapsulation, the protective film 112 is removed, as shownin FIG. 6, to expose the microelectronic device active surface 116,thereby forming a first substrate 130. As also shown in FIG. 6, theencapsulation material 122 is preferably forms at least one surface 124that is substantially planar to the microelectronic device activesurface 116 and the microelectronic substrate core first surface 106.The encapsulation material surface 124 may be utilized in furtherfabrication steps, along with the microelectronic substrate core firstsurface 106, as additional surface area for the formation ofinterconnection layers, such as dielectric material layers andconductive traces.

[0044] As shown in FIG. 7, a plurality of microelectronic devices 114 ofvarious sizes could be placed in each microelectronic substrate coreopening 104 and encapsulated with encapsulation material 122. It is alsounderstood that the microelectronic substrate core 102 is optional. Thefirst substrate 130 could be fabricated with the microelectronic devices114 merely encapsulated with encapsulation material 122, as shown inFIG. 8.

[0045]FIG. 9 illustrates a dual substrate assembly 132, according to thepresent invention, comprising the first substrate 130 attached to asecond substrate 130′. The second substrate 130′ has components similarto those illustrated for first substrate 130 in FIG. 6, wherein likecomponents are differentiated by a prime (′) designation. The firstsubstrate 130 and the second substrate 130′ are attached to one anothersuch that the first microelectronic substrate core second surface 108and the first microelectronic device back surfaces 118 are placedadjacent a second microelectronic substrate core second surface 108′ anda second microelectronic device back surface 118′ to form the dualsubstrate assembly 132. The attachment of the first substrate 130 to thesecond substrate 130′ may be achieved with a layer adhesive 134, or byany attachment technique as will be evident to those skilled in the art.While the first substrate 130 and the second substrate are shown forsimplicity to be exactly alike in FIG. 9, they do not have to be so.Similarly, for simplicity, FIGS. 10-17 (except FIG. 16) show symmetricalconfigurations. In practice, they could be dissimilar, as shown in FIG.16.

[0046] As shown in FIG. 10, at least one conductive via 136 is formedthrough the microelectronic substrate core 102 and the secondmicroelectronic substrate core 102′ by drilling holes therethrough andplating or filling the holes with a conductive material such as copper,aluminum, and the like. Such conductive vias 136 are used to achieveelectrical communication between at least one of the first substratemicroelectronic devices 114 and at least one of the second substratemicroelectronic devices 114′ and/or between microelectronic componentswhich may be mounted on interconnection layers which will be formed onthe microelectronic device active surfaces 116, 116′, themicroelectronic substrate core first surfaces 106, 106′, and theencapsulation material surfaces 124, 124′ of the first substrate 130 andthe second substrate 130′, respectively, as will be discussed. If thesubstrate core is made of a conductive material, a dielectric materialwill need to be disposed between the conducting material and theconductive via material, by one of various techniques which are known inthe art.

[0047] Although the following description relates to a bumpless,built-up layer technique for the formation of interconnection layers,the method of fabrication is not so limited. The interconnection layersmay be fabricated by a variety of techniques known in the art.

[0048]FIG. 11 illustrates an enlarged view of the dual substrateassembly 132 of FIG. 10, wherein the first substrate 130 and the secondsubstrate 130′ each have a microelectronic device (114, 114′)encapsulated within their microelectronic substrate cores (102, 102′),respectively. Each of the microelectronic device 114, 114′, of course,includes a plurality of electrical contacts 154, 154′ located on theirmicroelectronic device active surfaces 116, 116′, respectively. Theelectrical contacts 154, 154′ are electrically connected to circuitry(not shown) within each microelectronic device 114, 114′, respectively.Only four electrical contacts 154, 154′ are shown on eachmicroelectronic device 114, 114′ for sake of simplicity and clarity. Itis, of course, understood that any number of electrical contacts couldbe present.

[0049] As shown in FIG. 12, dielectric layers 156, 156′, and conductivetraces 158, 158′ are layered, respectively, over the microelectronicdevice active surface 116 (including the electrical contacts 154), themicroelectronic substrate core first surface 106, and the encapsulationmaterial surface 124. Dielectric layers 162, 162′, and conductive traces164, 164′ are layered, respectively, over the microelectronic deviceactive surface 116′ (including the electrical contacts 154′), themicroelectronic substrate core first surface 106′, and the encapsulationmaterial surface 124′. At least one conductive trace 158 may contact afirst via 136, which in turn contacts a conductive trace 164 to achieveelectrical contact between the first microelectronic device 114 and thesecond microelectronic device 114′.

[0050] The dielectric layers 156, 156′, 162, 162′ are preferably epoxyresin, polyimide, bisbenzocyclobutene, and the like, and more preferablyfilled epoxy resins available from Ibiden U.S.A. Corp., Santa Clara,Calif., U.S.A. and from Ajinomoto U.S.A., Inc., Paramus, N.J., U.S.A.The conductive traces 158, 158′, 164, 164′, may be any conductivematerial including, but not limited to, copper, aluminum, and alloysthereof. The formation of the dielectric layers 156, 156′, 162, 162′ maybe achieved by any known process, including but not limited tolamination, spin coating, roll coating, and spray-on deposition. Theconductive traces 158, 158′, 164, 164′ may extend through theirrespective dielectric layers 156, 156′, 162, 162′ to make electricalcontact with one another or with the electrical contacts 154, 154′. Thisis accomplish by forming vias through the dielectric layers 156, 156′,162, 162′ (after the formation of each dielectric layer), by any methodknown in the art, including but not limited to laser drilling andphotolithography (usually followed by an etch). The conductive traces158, 158′, 164, 164′ may be formed by any known technique, including butnot limited to semi-additive plating and photolithographic techniques.Preferably, corresponding dielectric layers (i.e., 156 and 162, 156′ and162′) and corresponding conductive traces (i.e., 158 and 164, 158′ and164′) are formed simultaneous on both the first substrate 130 and thesecond substrate 130′. However, it is understood that they could beformed independently on each substrate.

[0051] As shown in FIG. 13, conductive interconnects 166, 166′, such assolder bumps, solder balls, pins, and the like, may be formed to contactthe conductive traces 158′, 164′, respectively, and used forcommunication with external components (not shown). FIG. 13 illustratessolder bumps extending through solder resist dielectric layers 168, 168′to form a layered microelectronic substrate 170.

[0052] It is, of course, understood that a variety of interconnectionconfigurations may be devised. For example, as shown in the FIG. 13, atleast one conductive trace 164 may contact a second via 136′, which inturn contacts a conductive trace 158, 158′ to achieve electrical contactbetween the first microelectronic device 114 and the conductiveinterconnect 166 on an opposing side of the layered microelectronicsubstrate 170.

[0053]FIG. 14 illustrates a plurality of microelectronic devices 114,114′ respectively encapsulated with encapsulation material 122, 122′within the microelectronic substrate cores 102, 102′ to form the layeredmicroelectronic substrate 170 of the present invention. The layer(s) ofdielectric material and conductive traces comprising the interconnectionlayer is simply designated together as interconnection layers 172, 172′,respectively.

[0054] This interconnection layers 172, 172′ serve not only to formconnections between the microelectronic device 114, 114′ and/or theplurality of conductive interconnects 166, 166′, as described above, butalso to allow electrical communication among the microelectronic devices114 and among the microelectronic devices 114′.

[0055] As shown in FIG. 15, once the interconnection layers 172, 172′are formed, at least one microelectronic device 174 may be attached toan exposed surface 176 of the interconnection layer 172 by theconductive interconnects 166 and/or at least one microelectronic device174′ may be attached to an exposed surface 176′ of the interconnectionlayer 172′ by the conductive interconnects 166′. It is, of course,understood that the conductive interconnects 166, 166′ may be formedeither on the interconnection layer 172, 172′ (as shown in FIG. 11) oron the microelectronic devices 174, 174′. It is also understood that,although FIG. 15 illustrates the microelectronic devices 174, 174′ aspackaged flip-chips, the microelectronic devices may be any known activeor passive microelectronic devices including, but not limited to, logic(CPUs), memory (DRAM, SRAM, SDRAM, etc.), controllers (chip sets),capacitors, resistors, and the like. Furthermore, in addition toflip-chip attachment, as illustrated in FIG. 15, attachment of themicroelectronic devices 174, 174′ may be accomplished by other methods,such as wirebonding or other methods known to those skilled in the art.

[0056]FIG. 16 illustrates the assembly of FIG. 15 including a pluralityof the external attachment features 182, such as attach pins, solderballs (shown), or other such features, connected to the exposed surface176′ of the interconnection layer 172′. The external attachment features182 make electrical connection between the layered microelectronicsubstrate 170 and an external system board 184.

[0057] Of course, the layered microelectronic substrate 170 would bemost effective if the microelectronic devices 114, 114′ did not requireheat to be remove therefrom. However, if the microelectronic devices 114do need heat removal, a heat dissipation device 190 may be disposedbetween the first substrate 130 and the second substrate 130′, asillustrated FIG. 17. The heat dissipation device 190 may be a heat pipe,as known in the art, or a heat slug, such as a copper plate, an aluminumplate, a thermally conductive polymer, or a micro-electro-mechanical(MEMS) cooling system. The first substrate 130 and the second substrate130′ are preferably attached to the heat dissipation device 190 bylayers 192, 192′ of conductive adhesive material (respectively), such asthermally conductive epoxy, high thermal conductivity solder, and thelike. During the fabrication of the conductive vias 136, holes aredrilled through the first substrate 130, the heat dissipation device190, and the second substrate 130′. If the heat dissipation device 190is made of an electrically conductive material, the holes are coatedwith a thin conformal layer of dielectrical material 194, such as vapordeposition of a polymer, including but not limited to parylene. Anotherapproach known in the art is to fill the via holes with dielectricmaterial and drill a new smaller ole in the center. Thereafter, aspreviously discussed, a conductive material is plated or filled in theholes to form the conductive vias 136.

[0058]FIG. 18 illustrates an embodiment of a single substratemicroelectronic assembly 200, according to the present invention. Thesingle substrate microelectronic assembly 200 comprises a singlesubstrate 202 having a plurality of microelectronic devices 114encapsulated in a microelectronic substrate core 102, as previouslydiscussed. A plurality of the vias 136 is formed through the singlesubstrate 202. A first interconnection layer 204 is formed on themicroelectronic device active surfaces 116 and microelectronic substratecore first surface 106, and a second interconnection layer 204′ isformed on the microelectronic device back surfaces 118 andmicroelectronic substrate core first surface 108, preferably, in themanner previously discussed. At least one microelectronic device 174 maybe attached to an exposed surface 206 of the first interconnection layer204 by conductive interconnects 208 and/or at least one microelectronicdevice 174′ may be attached to the exposed surface 206′ of the secondinterconnection layer 204′ by conductive interconnects 208′.

[0059] If any of the embedded microelectronic devices 114 require heatremoval, heat dissipation devices 212 may be placed in thermal contactwith the microelectronic device back surfaces 118, as shown in FIG. 19.As part of the embedding process, the microelectronic device backsurface 118 is exposed either by proper choice of embedding process orby backside grinding, prior to forming the interconnection layer(s)(shown with second interconnection layer 204′). The microelectronicdevice back surface 118 is preferably metallized during the build-upprocess used to form the conductive traces (see discussion regardingFIG. 12) of the second interconnection layer 204′when a metal is used.The metallized surfaces are illustrated as elements 214. The metallizedsurfaces 214 may be formed by having an open area of the dielectricpatterning mask or by ablating away all of dielectric with a laser ateach layering step, as previously discussed. Of course, othertechniques, as will be known to those skilled in the art, may beutilized.

[0060] As shown in FIG. 20, more than one single substratemicroelectronic substrate assembly 200, as shown in FIG. 19, may belayered to form a layered microelectronic substrate assembly, accordingto the present invention. The layered microelectronic assembly 220 isfabricated by orienting a first single substrate microelectronicsubstrate assembly 200′ to a second single substrate microelectronicsubstrate assembly 200″, such that the microelectronic device activesurfaces 116′ and 116″, respectively, face one another. Theinterconnection layers 222′ and 222″, which are formed on themicroelectronic device active surfaces 116′ and 116″ and the substratecore first surfaces 106′ and 106′ respectively, may be electricallyinterconnected by direct lamination, by a plurality of conductiveinterconnects 226, such as solder balls (shown), or by any othertechnique as will be known to those skilled in the art.

[0061] Interconnection layers 224′ and 224″ are formed on themicroelectronic device back surfaces 118 ′ and 118″, and microelectronicsubstrate core second surface 108′ and 108″, respectively, in the mannerpreviously discussed. At least one microelectronic device 174′ may beattached to an exposed surface 228′ of the interconnection layers 224′by conductive interconnections 208′ and/or at least one microelectronicdevice 174″ may be attached to the exposed surface 228″ of theinterconnection layer 224″ by conductive interconnections 208″. Ofcourse, heat dissipation devices 212′ and 212″ (not shown) may be placedin thermal contact with the microelectronic device back surfaces 118′and 118″, respectively. As previously discussed, a plurality of the vias136′ and 136″ may formed through the first microelectronic substratecore 102′ and the second microelectronic substrate core 102″,respectively.

[0062] It is, of course, understood that the interconnection layers 224′and 224″ are optional, as shown in FIG. 21, wherein thermal dissipationdevices 212′ and 212″ may be attached directly to the microelectronicdevice back surfaces 118 ′ and 118″. Further, as shown in FIG. 21, ifmicroelectronic components, such as decoupling capacitors 234, need tobe located close to a particular microelectronic device, such asmicroelectronic device 114′. Thus, they may be positioned withinmicroelectronic substrate assembly 200″ directly opposite themicroelectronic device 114′. Of course, an equivalent arrangement (notshown) is possible for placing components near dice 212″ by embeddingthem in the opposite microelectronic substrate assembly 200′.

[0063] Furthermore, as shown in FIG. 22, the heat dissipation devices212′ and 212″ and the first microelectronic substrate core 102′ and thesecond microelectronic substrate core 102″ may be replaced by a firstthermally conductive microelectronic substrate core 236′ and a secondthermally conductive microelectronic substrate core 236″. Themicroelectronic device 114′ is disposed within a cavity in the firstthermally conductive microelectronic substrate core 236′ and theencapsulation material 122′ fills any voids between the microelectronicdevice 114′ and the first microelectronic substrate core 102′. Themicroelectronic device 114′ may be secured with a thermally conductiveadhesive or solder, or may merely be secured with the encapsulationmaterial 122′. The microelectronic devices 114″ and the microelectroniccomponents 234 are shown likewise situated in cavities in the secondthermally conductive microelectronic substrate core 236″.

[0064] It is understood that the assemblies of FIGS. 17-22 may includeexternal attachment features (see elements 182 in FIG. 16), such asattach pins, solder balls, edge connectors, or other such features (notshown), connected to an external system board (not shown), such as isshown in FIG. 16.

[0065] Having thus described in detail embodiments of the presentinvention, it is understood that the invention defined by the appendedclaims is not to be limited by particular details set forth in the abovedescription, as many apparent variations thereof are possible withoutdeparting from the spirit or scope thereof.

What is claimed is:
 1. A microelectronic substrate, comprising: a firstmicroelectronic substrate core having a first surface and an opposingsecond surface, said first microelectronic substrate core having atleast one opening defined therein extending from said firstmicroelectronic substrate core first surface to said firstmicroelectronic substrate core second surface; at least one firstmicroelectronic device disposed within said at least one opening, saidat least one first microelectronic device having an active surface and aback surface, wherein said first microelectronic device active surfaceis adjacent said first microelectronic substrate core first surface; anencapsulation material adhering said first microelectronic substratecore to said at least one first microelectronic device forming a firstsurface adjacent said microelectronic die active surface and said corefirst surface and a second surface adjacent said microelectronic dieback surface and said core second surface; and at least one conductivevia extending from said first microelectronic substrate core firstsurface to said first microelectronic substrate core second surface. 2.The microelectronic substrate of claim 1, further including a firstinterconnection layer disposed proximate said first microelectronicsubstrate core first surface and said first microelectronic deviceactive surface and further including a second interconnection layerdisposed proximate said first microelectronic substrate core secondsurface and said first microelectronic device back surface, wherein saidat least one conductive via electrically connects said firstinterconnection layer and said second interconnection layer.
 3. Themicroelectronic substrate of claim 2, further including at least onemicroelectronic device attached to at least one of said firstinterconnection layer and said second interconnection layers.
 4. Themicroelectronic substrate of claim 2, further including at least oneheat dissipation device thermally attached to said at least onemicroelectronic device back surface.
 5. The microelectronic substrate ofclaim 2, wherein said first interconnection layer comprises at least onedielectric layer abutting at least one of said first microelectronicdevice active surface, said first microelectronic substrate core firstsurface, and said encapsulation material first surface, and at least oneconductive trace disposed on said at least one dielectric layer.
 6. Themicroelectronic substrate of claim 5, wherein said at least oneconductive trace extends through said at least one dielectric layer tocontact at least one electrical contact on said first microelectronicdevice active surface.
 7. The microelectronic substrate of claim 5,wherein said at least one conductive trace extends through said at leastone dielectric layer to contact said at least one conductive via.
 8. Themicroelectronic substrate of claim 2, wherein said secondinterconnection layer comprises at least one dielectric layer abuttingat least one of said microelectronic device back surface, saidmicroelectronic substrate core second surface, and said encapsulantmaterial second surface, and at least one conductive trace disposed onsaid at least one dielectric layer.
 9. The microelectronic substrate ofclaim 8, wherein said at least one conductive trace extends through saidat least one dielectric layer to contact said at least one conductivevia.
 10. The microelectronic substrate of claim 1, further including: asecond microelectronic substrate core having a first surface and anopposing second surface, said second microelectronic substrate corehaving at least one opening defined therein extending from said secondmicroelectronic substrate core first surface to said secondmicroelectronic substrate core second surface; at least one secondmicroelectronic device disposed within said at least one opening, saidat least one second microelectronic device having an active surfaceadjacent said second microelectronic substrate core first surface and aback surface adjacent said second microelectronic substrate core secondsurface; an encapsulation material adhering said second microelectronicsubstrate core to said at least one second microelectronic deviceforming a first surface adjacent said microelectronic die active surfaceand said core first surface and a second surface adjacent saidmicroelectronic die back surface and said core second surface; saidfirst microelectronic substrate core second surface attached to saidsecond microelectronic substrate core second surface; and said at leastone conductive via extends from said first microelectronic substratecore first surface to said second microelectronic substrate core firstsurface.
 11. The microelectronic substrate of claim 10, furtherincluding a heat dissipation device disposed between said firstmicroelectronic substrate core second surface and said secondmicroelectronic substrate core second surface.
 12. The microelectronicsubstrate of claim 11, further including a dielectric material disposedbetween said conductive via and said heat dissipation device.
 13. Amicroelectronic substrate, comprising: at least one firstmicroelectronic device having an active surface and a back surface; anencapsulation material forming a first surface adjacent saidmicroelectronic die active surface and a second surface adjacent saidmicroelectronic die back surface; and at least one conductive viaextending from said encapsulation material first surface to saidencapsulation material second surface.
 14. The microelectronic substrateof claim 13, further including a first interconnection layer disposedproximate said encapsulation material first surface and said firstmicroelectronic device active surface and further including a secondinterconnection layer disposed proximate said encapsulation materialsecond surface and said first microelectronic device back surface,wherein said at least one conductive via electrically connects saidfirst interconnection layer and said second interconnection layer.
 15. Amicroelectronic substrate, comprising: a first microelectronic substratecore having a first surface and an opposing second surface, said firstmicroelectronic substrate core having at least one opening definedtherein extending from said first microelectronic substrate core firstsurface to said first microelectronic substrate core second surface; atleast one first microelectronic device disposed within said at least oneopening, said at least one first microelectronic device having an activesurface and a back surface, wherein said first microelectronic deviceactive surface is adjacent said first microelectronic substrate corefirst surface; a first encapsulation material adhering said firstmicroelectronic substrate core to said at least one firstmicroelectronic device forming a first surface adjacent saidmicroelectronic die active surface and said core first surface and asecond surface adjacent said microelectronic die back surface and saidcore second surface; a second microelectronic substrate core having afirst surface and an opposing second surface, said secondmicroelectronic substrate core having at least one opening definedtherein extending from said second microelectronic substrate core firstsurface to said second microelectronic substrate core second surface; atleast one second microelectronic device disposed within said at leastone opening, said at least one second microelectronic device having anactive surface and a back surface, wherein said second microelectronicdevice active surface is adjacent said second microelectronic substratecore first surface; a second encapsulation material adhering said secondmicroelectronic substrate core to said at least one secondmicroelectronic device forming a first surface adjacent saidmicroelectronic die active surface and said core first surface and asecond surface adjacent said microelectronic die back surface and saidcore second surface; and said first microelectronic device activesurface oriented to face said second microelectronic device activesurface.
 16. The microelectronic substrate of claim 15, furtherincluding a first interconnection layer disposed proximate said firstmicroelectronic substrate core first surface, said first encapsulationfirst surface, and said first microelectronic device active surface andfurther including a second interconnection layer disposed proximate saidsecond microelectronic substrate core first surface, said secondencapsulation material first surface, and said first microelectronicdevice active surface, wherein said first and second interconnectionlayers are electrically connected.
 17. The microelectronic substrate ofclaim 15, further including an interconnection layer disposed proximateat least one of said first microelectronic substrate core secondsurface, said first encapsulation material second surface, and saidfirst microelectronic device back surface, and said secondmicroelectronic substrate core second surface, said second encapsulationmaterial second surface, and said second microelectronic device backsurface.
 18. The microelectronic substrate of claim 15, furtherincluding at least one conductive via extending from said firstmicroelectronic substrate core first surface and said firstmicroelectronic substrate core second surface.
 19. The microelectronicsubstrate of claim 15, further including at least one conductive viaextending between said second microelectronic substrate core firstsurface and said second microelectronic substrate core second surface.20. The microelectronic substrate of claim 15, further including atleast one conductive via extending from said first microelectronicsubstrate core second surface and said second microelectronic substratecore second surface.
 21. The microelectronic substrate of claim 15,further including at least one heat dissipation device thermallyattached to at least one of said at least one first microelectronicdevice back surface and said at least one second microelectronic deviceback surface.
 22. A microelectronic substrate, comprising: a firstmicroelectronic substrate core having a first surface and an opposingsecond surface, said first microelectronic substrate core having atleast one cavity defined therein; at least one first microelectronicdevice disposed within said at least one cavity, said at least one firstmicroelectronic device having an active surface and a back surface,wherein said first microelectronic device active surface is adjacentsaid first microelectronic substrate core first surface; a firstencapsulation material adhering said first microelectronic substratecore to said at least one first microelectronic device forming a firstsurface adjacent said microelectronic die active surface; a secondmicroelectronic substrate core having a first surface and an opposingsecond surface, said second microelectronic substrate core having atleast one cavity defined therein; at least one second microelectronicdevice disposed within said at least one cavity, said at least onesecond microelectronic device having an active surface and a backsurface, wherein said second microelectronic device active surface isadjacent said second microelectronic substrate core first surface; asecond encapsulation material adhering said second microelectronicsubstrate core to said at least one second microelectronic deviceforming a first surface adjacent said microelectronic die active surfaceand said core first surface; and said first microelectronic deviceactive surface oriented to face said second microelectronic deviceactive surface.
 23. The microelectronic substrate of claim 22, furtherincluding a first interconnection layer disposed proximate said firstmicroelectronic substrate core first surface, said first encapsulationfirst surface, and said first microelectronic device active surface andfurther including a second interconnection layer disposed proximate saidsecond microelectronic substrate core first surface, said secondencapsulation material first surface, and said first microelectronicdevice active surface, wherein said first and second interconnectionlayers are electrically connected.
 24. A method of fabricating amicroelectronic substrate, comprising: providing a first microelectronicsubstrate core having a first surface and an opposing second surface,said first microelectronic substrate core having at least one openingdefined therein extending from said first microelectronic substrate corefirst surface to said first microelectronic substrate core secondsurface; disposing at least one first microelectronic device having anactive surface and a back surface within said at least one opening suchthat said first microelectronic device active surface resides adjacentsaid first microelectronic substrate core first surface; disposing anencapsulation material in said at least one opening to adhere said firstmicroelectronic substrate core to said at least one firstmicroelectronic device and forming a first surface adjacent saidmicroelectronic die active surface and a second surface adjacent saidmicroelectronic die back surface; and forming at least one conductivevia to extend from said first microelectronic substrate core first tosaid first microelectronic substrate core second surface.
 25. The methodof claim 24, further including thermally attaching at least one heatdissipation device to at least one microelectronic device back surface.26. The method of claim 24, further including: forming a firstinterconnection layer disposed proximate said first microelectronicsubstrate core first surface, said encapsulation material first surface,and said first microelectronic device active surface; forming a secondinterconnection layer disposed proximate said first microelectronicsubstrate core second surface, said encapsulation material secondsurface, and said first microelectronic device back surface.
 27. Themethod of claim 26, wherein forming said first interconnection layercomprises: forming at least one dielectric material layer on at least aportion of said first microelectronic device active surface, saidencapsulation material first surface, and said microelectronic substratecore first surface; forming at least one via through said at least onedielectric material layer to expose a portion of said microelectronicdevice active surface; and forming at least one conductive trace on saidat least one dielectric material layer which extends into said at leastone via to electrically contact said first microelectronic device activesurface.
 28. The method of claim 27, wherein forming at least oneconductive trace comprises forming said at least one conductive trace toextend through said at least one dielectric layer to contact said atleast one conductive via.
 29. The method of claim 26, wherein formingsaid second interconnection layer comprises: forming at least onedielectric material layer on at least a portion of said firstmicroelectronic device back surface, said encapsulation material secondsurface, and said microelectronic substrate core second surface; formingat least one via through said at least one dielectric material layer;and forming at least one conductive trace on said at least onedielectric material layer which extends into said at least one via toelectrically contact said conductive via.
 30. The method of claim 24,further including: providing a second microelectronic substrate corehaving a first surface and an opposing second surface, said secondmicroelectronic substrate core having at least one opening definedtherein extending from said second microelectronic substrate core firstsurface to said second microelectronic substrate core second surface;disposing at least one second microelectronic device within said atleast one opening, such that an active surface of said at least onesecond microelectronic device resides adjacent said secondmicroelectronic substrate core first surface and such that a backsurface of said at least one second microelectronic device residesadjacent said second microelectronic substrate core second surface;disposing an encapsulation material in said opening to adhere saidsecond microelectronic substrate core to said at least one secondmicroelectronic device; attaching said first microelectronic substratecore second surface to said second microelectronic substrate core secondsurface; and forming said at least one conductive via to extend fromsaid first microelectronic substrate core first surface to said secondmicroelectronic substrate core first surface.
 31. The method of claim30, further including disposing a heat dissipation device between saidfirst microelectronic substrate core second surface and said secondmicroelectronic substrate core second surface.
 32. The method of claim30, further including forming at least one conductive viainterconnecting said first microelectronic substrate core first surfaceand said second microelectronic substrate core first surface.
 33. Themethod of claim 32, further including disposing a dielectric materialbetween said at least one conductive via and said heat dissipationdevice.
 34. The method of claim 24, further including abutting saidfirst microelectronic substrate core first surface and said firstmicroelectronic device active surface against a protective film prior todisposing said encapsulation material in said at least one opening. 35.The method of claim 34, wherein abutting said microelectronic substratecore first surface and said at least one microelectronic device activesurface against a protective film comprises abutting said firstmicroelectronic substrate core first surface and said firstmicroelectronic device active surface against an adhesive layer on saidprotective film prior to disposing said encapsulation material in saidat least one opening.
 36. A method of fabricating a microelectronicsubstrate, comprising: providing a first microelectronic substrate corehaving a first surface and an opposing second surface, said firstmicroelectronic substrate core having at least one opening definedtherein extending from said first microelectronic substrate core firstsurface to said first microelectronic substrate core second surface;disposing at least one first microelectronic device having an activesurface and a back surface within said at least one opening such thatsaid first microelectronic device active surface resides adjacent saidfirst microelectronic substrate core first surface; disposing a firstencapsulation material in said microelectronic substrate core openingadhering said first microelectronic substrate core to said at least onefirst microelectronic device, forming a first surface adjacent saidfirst microelectronic die active surface and a second surface adjacentsaid first microelectronic die back surface; providing a secondmicroelectronic substrate core having a first surface and an opposingsecond surface, said second microelectronic substrate core having atleast one opening defined therein extending from said secondmicroelectronic substrate core first surface to said secondmicroelectronic substrate core second surface; disposing at least onesecond microelectronic device having an active surface and a backsurface within said at least one opening such that said secondmicroelectronic device active surface resides adjacent said secondmicroelectronic substrate core first surface; disposing a secondencapsulation material in said second microelectronic core openingadhering said second microelectronic substrate core to said at least onesecond microelectronic device, forming a first surface adjacent saidsecond microelectronic active surface and a second surface adjacent saidmicroelectronic die back surface; and attaching said firstmicroelectronic core to said second microelectronic core such that saidfirst microelectronic device active surface oriented to face said secondmicroelectronic device active surface.
 37. The method of claim 36,further including forming an interconnection layer disposed proximatesaid first microelectronic substrate core first surface, said firstencapsulation material first surface, and said first microelectronicdevice active surface and further including forming a secondinterconnection layer disposed proximate said second microelectronicsubstrate core first surface, said second encapsulation material firstsurface, and said first microelectronic device active surface; andwherein said attaching said first microelectronic core to said secondmicroelectronic core includes forming electrical connections betweensaid first and second interconnection layers.
 38. The method of claim36, further including forming an interconnection layer disposedproximate at least one of said first microelectronic substrate coresecond surface, said first encapsulation material second surface, andsaid first microelectronic device back surface, and said secondmicroelectronic substrate core second surface, said second encapsulationmaterial second surface, and said second microelectronic device backsurface.
 39. The method of claim 36, further including forming at leastone conductive via to extend from said first microelectronic substratecore first surface and said first microelectronic substrate core secondsurface.
 40. The method of claim 36, further forming including at leastone conductive via to extend from said second microelectronic substratecore first surface and said second microelectronic substrate core secondsurface.
 41. The method of claim 36, further including forming at leastone conductive via interconnecting said first microelectronic substratecore second surface and said second microelectronic substrate coresecond surface.
 42. The method of claim 36, further including thermallyattaching at least one heat dissipation device to at least one of saidat least one first microelectronic device back surface and said at leastone second microelectronic device back surface.
 43. The method of claim42, further including forming at least one conductive viainterconnecting said first microelectronic substrate core first surfaceand said second microelectronic substrate core first surface.
 44. Themethod of claim 43, further including disposing a dielectric materialbetween said at least one conductive via and said heat dissipationdevice.